Data storage devices such as disk drives comprise a disk and a head connected to a distal end of an actuator arm which is rotated about a pivot by a voice coil motor (VCM) to position the head radially over the disk. The disk comprises a plurality of radially spaced, concentric tracks for recording user data sectors and servo sectors. The servo sectors comprise head positioning information (e.g., a track address) which is read by the head and processed by a servo control system to control the actuator arm as it seeks from track to track.
Data is typically written to the disk by modulating a write current in an inductive coil to record magnetic transitions onto the disk surface in a process referred to as saturation recording. During read-back, the magnetic transitions are sensed by a read element (e.g., a magneto-resistive element) and the resulting read signal demodulated by a suitable read channel. Heat assisted magnetic recording (HAMR) and microwave assisted magnetic recording (MAMR) are recent developments that improve the quality of written data by heating the disk surface during write operations in order to decrease the coercivity of the magnetic medium, thereby enabling the magnetic field generated by the write coil to more readily magnetize the disk surface.
An air bearing forms between the head and the disk due to the disk rotating at high speeds. Since the quality of the write/read signal depends on the fly height of the head, conventional heads (e.g., magneto-resistive heads) may comprise an actuator for controlling the fly height. Any suitable dynamic fly height (DFH) actuator may be employed, such as a heater which controls fly height through thermal expansion, or a piezoelectric (PZT) actuator. The fly height may also be affected by other expansive components of the head, such as when a near field transducer (NFT) protrudes toward the disk while heating the disk with a laser (HAMR). Accordingly, it is desirable to determine the appropriate DFH setting (e.g., appropriate current applied to a heater) that achieves the target fly height for the head during write and read operations. To this end, a touchdown sensor may be integrated into the head for determining the DFH setting that causes a component of the head (e.g., the NFT) to contact the disk surface.
FIG. 1A shows a prior art disk drive comprising a head 2 having an integrated touchdown sensor 4, and control circuitry 6 comprising a differential amplifier 8 configured to sense a voltage change across the touchdown sensor 4. The touchdown sensor 4 is coupled to the control circuitry 6 over two lead lines each connected to a respective end of the touchdown sensor 4. A control voltage 10 is applied to one end of the touchdown sensor 4 in order to bias the sensor so that it operates in a linear range. The touchdown sensor 4 may be a thermistor having a resistance that varies with a decreasing fly height and/or as the head contacts the disk surface. The resulting change in resistance is transduced into a single-ended output 12 voltage output by the differential amplifier 8.
FIG. 1B shows prior art control circuitry 6 for generating the single-ended output 12 representing the response of the touchdown sensor 4. The control circuitry 6 comprises a common-gate differential amplifier with a bias voltage 14 in series with the common-gates which generates a corresponding bias voltage across the touchdown sensor 4. A current source 161 and 162 biases each leg of the common-gate differential amplifier to cancel the effect of the bias current from the bias voltage 14, thereby achieving a zero-reference point for the single-ended differential output 12 (i.e., a quiescent state). A control voltage 18 biases the gates of the transistors 201 and 202 to set the voltage of Rsense 14 with respect to the ground potential. The control voltage 18 is coupled to the plus terminal side (+) of the differential amplifier, but in other embodiments it can be coupled to the negative terminal side (−), or as a common-mode voltage of the amplifier's input.
The small signal response of the control circuitry 6 shown in FIG. 1B can be described as:
            V      out        =                  V                  i          ⁢                                          ⁢          n                    *      G      ⁢                          ⁢      1            Vin    =                  Δ        ⁢                                  ⁢        Rsense        *        Ibias        *        2        *        RL        *        gm                    2        +                  gm          *          Rsense                    where gm is the conductance of the transistors.